Search - verilog RAM

[VHDL-FPGA-Verilog] VeriRISC_CPU_Verilog

Description: Verilog硬件描述语言实现VeriRISC CPU。模块包含：8位寄存器，5位计数器，32*8 RAM，8位ALU，MUX，顺序控制器，时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clock generator. Testbench is included.
Platform: | Size: 9216 | Author: 张昊溢 | Hits:

[VHDL-FPGA-Verilog] 32_by_8_RAM

Description: 32*8 RAM。Verilog实现。包含TB。-32 by 8 RAM. Testbench included.
Platform: | Size: 3072 | Author: 张昊溢 | Hits:

[VHDL-FPGA-Verilog] fpgaaverilogamaxamin

Description: verilog 编写的比较最大值最小值得的程序，而且能够求出最大最小值在ram中存储的位置，测试通过下载即用-Comparison of the maximum write verilog smallest worthwhile program, and minimum and maximum values can be obtained is stored in ram position, the test that is used by downloading
Platform: | Size: 3072 | Author: | Hits:

[VHDL-FPGA-Verilog] bram_16x8_top

Description: 使用Verilog语言编写的RAM程序,可以双向读写,在Xilinx Spartan-6上运行通过,是很好的Verlog程序-RAM using Verilog language program, you can bi-literacy, in the Xilinx Spartan-6 run through, is a very good program Verlog
Platform: | Size: 9216 | Author: 于洋 | Hits:

[VHDL-FPGA-Verilog] LPM_RAM

Description: verilog 参数可设置调用模块RAM-verilog parameter can be set to call the module RAM
Platform: | Size: 146432 | Author: water | Hits:

[VHDL-FPGA-Verilog] idt723641

Description: VERILOG双端口驱动IDT的双扣RAM很好用的-VERILOG Twill the IDT dual-port RAM drive good use
Platform: | Size: 14336 | Author: hehh | Hits:

[Other] try_ram

Description: Verilog Codes for RAM-Testing. Write data in the RAM and read it out from the RAM. Tested on NEXYS 3.
Platform: | Size: 829440 | Author: Di Yu | Hits:

[VHDL-FPGA-Verilog] 9288Test3

Description: AD9288 100MhzAD转换芯片的控制代码，用Verilog语言实现。采集数据存储于FPGA内置RAM中。-Conversion chip AD9288 100MhzAD control code, using Verilog language. FPGA collected data is stored in the built-in RAM.
Platform: | Size: 2275328 | Author: xiexin | Hits:

[VHDL-FPGA-Verilog] DW8051

Description: verilog代码，51内核，是DW8051，8K ram 64K rom强大版本-verilog code, 51 cores, is DW8051, 8K ram 64K rom powerful version
Platform: | Size: 72704 | Author: 张文海 | Hits:

[Other] RF128x32

Description: 基于verilog的128*32RAM设计代码-The RAM-based design code verilog
Platform: | Size: 67584 | Author: Paul | Hits:

[VHDL-FPGA-Verilog] ram_test

Description: 基于Verilog的存储器模块及其测试模块-a ram module based on Verilog HDL
Platform: | Size: 3072 | Author: 刘瀚珅 | Hits:

[VHDL-FPGA-Verilog] ddr3_uniphy_siv_example_restored

Description: A system that is written in Verilog to be able to read and write data to a DDR3 RAM by Altera FPGA
Platform: | Size: 19305472 | Author: Kaan Mutlu | Hits:

[VHDL-FPGA-Verilog] syncram

Description: verilog rtl and testbench code for single port sync ram
Platform: | Size: 1024 | Author: murali krishna | Hits:

[Other] shuangkouRAM

Description: verilog语言，调用FPGA内部配置的双口RAM，并控制采集-verilog language, calling FPGA internal configuration of dual-port RAM, and control the collection
Platform: | Size: 3710976 | Author: 章金敏 | Hits:

[VHDL-FPGA-Verilog] asyn_fifo

Description: 本文同步FIFO为TPRAM（两端口RAM，一读一写）。有详细verilog 程序以及说明-FIFO divided by clock domain can be divided into synchronous and asynchronous FIFO FIFO, FIFO read and write only one clock synchronous, asynchronous FIFO read and write were a clock. FIFO divided by port can be divided into TPRAM, DPRAM, TPRAM read one each port, a port read-only, write-only another port, DPRAM read each one each port, each port can either be read. This article synchronous FIFO is TPRAM (two-port RAM, a read a write).
Platform: | Size: 650240 | Author: jodyql | Hits:

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